Infineon /XMC4200 /USIC0_CH0 /SCTR

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Interpret as SCTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)SDIR 0 (value1)PDL 0 (value1)DSM0 (value1)HPCDIR 0 (value1)DOCFG 0 (value1)TRM0FLE0 (value1)WLE

TRM=value1, PDL=value1, HPCDIR=value1, DSM=value1, SDIR=value1, WLE=value1, DOCFG=value1

Description

Shift Control Register

Fields

SDIR

Shift Direction

0 (value1): Shift LSB first. The first data bit of a data word is located at bit position 0.

1 (value2): Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE.

PDL

Passive Data Level

0 (value1): The passive data level is 0.

1 (value2): The passive data level is 1.

DSM

Data Shift Mode

0 (value1): Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0.

2 (value3): Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT[1:0] respectively.

3 (value4): Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX[5:3]) and DOUT[3:0] respectively.

HPCDIR

Port Control Direction

0 (value1): The pin(s) with hardware pin control enabled are selected to be in input mode.

1 (value2): The pin(s) with hardware pin control enabled are selected to be in output mode.

DOCFG

Data Output Configuration

0 (value1): DOUTx = shift data value

1 (value2): DOUTx = inverted shift data value

TRM

Transmission Mode

0 (value1): The shift control signal is considered as inactive and data frame transfers are not possible.

1 (value2): The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers.

2 (value3): The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal.

3 (value4): The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal.

FLE

Frame Length

WLE

Word Length

0 (value1): The data word contains 1 data bit located at bit position 0.

1 (value2): The data word contains 2 data bits located at bit positions [1:0].

14 (value3): The data word contains 15 data bits located at bit positions [14:0].

15 (value4): The data word contains 16 data bits located at bit positions [15:0].

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