Infineon /XMC4200 /VADC /CLC

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)DISR 0 (value1)DISS 0 (value1)EDIS

DISS=value1, DISR=value1, EDIS=value1

Description

Clock Control Register

Fields

DISR

Module Disable Request Bit

0 (value1): On request: enable the module clock

1 (value2): Off request: stop the module clock

DISS

Module Disable Status Bit

0 (value1): Module clock is enabled

1 (value2): Off: module is not clocked

EDIS

Sleep Mode Enable Control

0 (value1): Sleep mode request is enabled and functional

1 (value2): Module disregards the sleep mode control signal

Links

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