Regviz

Infineon /XMC4200 /VADC /OCS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as OCS

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Infineon/XMC4200/VADC/OCS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)TGS0 (value1)TGB 0 (TG_P)TG_P 0 (value1)SUS0 (SUS_P)SUS_P 0 (value1)SUSSTA

SUSSTA=value1, TGS=value1, SUS=value1, TGB=value1

Description

OCDS Control and Status Register

Fields

TGS

Trigger Set for OTGB0/1

0 (value1): No Trigger Set output

1 (value2): Trigger Set 1: TS16_SSIG, input sample signals
TGB

OTGB0/1 Bus Select

0 (value1): Trigger Set is output on OTGB0

1 (value2): Trigger Set is output on OTGB1
TG_P

TGS, TGB Write Protection
SUS

OCDS Suspend Control

0 (value1): Will not suspend

1 (value2): Hard suspend: Clock is switched off immediately.

2 (value3): Soft suspend mode 0: Stop conversions after the currently running one is completed and its result has been stored. No change for the arbiter.

3 (value4): Soft suspend mode 1: Stop conversions after the currently running one is completed and its result has been stored. Stop arbiter after the current arbitration round.
SUS_P

SUS Write Protection
SUSSTA

Suspend State

0 (value1): Module is not (yet) suspended

1 (value2): Module is suspended

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data