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Infineon /XMC4200 /VADC_G0 /SYNCTR

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Interpret as SYNCTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)STSEL 0 (value1)EVALR1 0 (value1)EVALR2 0 (value1)EVALR3

EVALR3=value1, EVALR1=value1, EVALR2=value1, STSEL=value1

Description

Synchronization Control Register

Fields

STSEL

Start Selection

0 (value1): Kernel is synchronization master: Use own bitfield GxARBCFG.ANONC

1 (value2): Kernel is synchronization slave: Control information from input CI1

2 (value3): Kernel is synchronization slave: Control information from input CI2

3 (value4): Kernel is synchronization slave: Control information from input CI3
EVALR1

Evaluate Ready Input Rx

0 (value1): No ready input control

1 (value2): Ready input Rx is considered for the start of a parallel conversion of this conversion group
EVALR2

Evaluate Ready Input Rx

0 (value1): No ready input control

1 (value2): Ready input Rx is considered for the start of a parallel conversion of this conversion group
EVALR3

Evaluate Ready Input Rx

0 (value1): No ready input control

1 (value2): Ready input Rx is considered for the start of a parallel conversion of this conversion group

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data