Infineon /XMC4400 /ETH0 /DEBUG

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Interpret as DEBUG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RPESTS)RPESTS 0RFCFCSTS 0 (RWCSTS)RWCSTS 0RRCSTS 0RXFSTS 0 (TPESTS)TPESTS 0TFCSTS 0 (TXPAUSED)TXPAUSED 0TRCSTS 0 (TWCSTS)TWCSTS 0 (TXFSTS)TXFSTS 0 (TXSTSFSTS)TXSTSFSTS

Description

Debug Register

Fields

RPESTS

MAC MII Receive Protocol Engine Status

RFCFCSTS

MAC Receive Frame Controller FIFO Status

RWCSTS

MTL Rx FIFO Write Controller Active Status

RRCSTS

MTL Rx FIFO Read Controller State

RXFSTS

MTL Rx FIFO Fill-level Status

TPESTS

MAC MII Transmit Protocol Engine Status

TFCSTS

MAC Transmit Frame Controller Status

TXPAUSED

MAC transmitter in PAUSE

TRCSTS

MTL Tx FIFO Read Controller Status

TWCSTS

MTL Tx FIFO Write Controller Active Status

TXFSTS

MTL Tx FIFO Not Empty Status

TXSTSFSTS

MTL TxStatus FIFO Full Status

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