Infineon /XMC4400 /ETH0 /HW_FEATURE

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Interpret as HW_FEATURE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MIISEL)MIISEL 0 (GMIISEL)GMIISEL 0 (HDSEL)HDSEL 0 (EXTHASHEN)EXTHASHEN 0 (HASHSEL)HASHSEL 0 (ADDMACADRSEL)ADDMACADRSEL 0 (PCSSEL)PCSSEL 0 (L3L4FLTREN)L3L4FLTREN 0 (SMASEL)SMASEL 0 (RWKSEL)RWKSEL 0 (MGKSEL)MGKSEL 0 (MMCSEL)MMCSEL 0 (TSVER1SEL)TSVER1SEL 0 (TSVER2SEL)TSVER2SEL 0 (EEESEL)EEESEL 0 (AVSEL)AVSEL 0 (TXCOESEL)TXCOESEL 0 (RXTYP1COE)RXTYP1COE 0 (RXTYP2COE)RXTYP2COE 0 (RXFIFOSIZE)RXFIFOSIZE 0RXCHCNT 0TXCHCNT 0 (ENHDESSEL)ENHDESSEL 0 (INTTSEN)INTTSEN 0 (FLEXIPPSEN)FLEXIPPSEN 0 (SAVLANINS)SAVLANINS 0ACTPHYIF

Description

HW Feature Register

Fields

MIISEL

10 or 100 Mbps support

GMIISEL

1000 Mbps support

HDSEL

Half-Duplex support

EXTHASHEN

Expanded DA Hash Filter

HASHSEL

HASH Filter

ADDMACADRSEL

Multiple MAC Address Registers

PCSSEL

PCS registers (TBI, SGMII, or RTBI PHY interface)

L3L4FLTREN

Layer 3 and Layer 4 Filter Feature

SMASEL

SMA (MDIO) Interface

RWKSEL

PMT Remote Wakeup

MGKSEL

PMT Magic Packet

MMCSEL

RMON Module

TSVER1SEL

Only IEEE 1588-2002 Timestamp

TSVER2SEL

IEEE 1588-2008 Advanced Timestamp

EEESEL

Energy Efficient Ethernet

AVSEL

AV Feature

TXCOESEL

Checksum Offload in Tx

RXTYP1COE

IP Checksum Offload (Type 1) in Rx

RXTYP2COE

IP Checksum Offload (Type 2) in Rx

RXFIFOSIZE

Rx FIFO > 2,048 Bytes

RXCHCNT

Number of additional Rx channels

TXCHCNT

Number of additional Tx channels

ENHDESSEL

Alternate (Enhanced Descriptor)

INTTSEN

Timestamping with Internal System Time

FLEXIPPSEN

Flexible Pulse-Per-Second Output

SAVLANINS

Source Address or VLAN Insertion

ACTPHYIF

Active or Selected PHY interface

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