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Infineon /XMC4400 /HRPWM0 /CSGSETG

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Interpret as CSGSETG

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https://regviz.com/r/Infineon/XMC4200/HRPWM0/CSGSETG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SD0R)SD0R 0 (SC0R)SC0R 0 (SC0P)SC0P 0 (SD1R)SD1R 0 (SC1R)SC1R 0 (SC1P)SC1P 0 (SD2R)SD2R 0 (SC2R)SC2R 0 (SC2P)SC2P

Description

Global CSG run bit set

Fields

SD0R

DAC0 run bit set
SC0R

CMP0 run bit set
SC0P

CMP0 passive level set
SD1R

DAC1 run bit set
SC1R

CMP1 run bit set
SC1P

CMP1 passive level set
SD2R

DAC2 run bit set
SC2R

CMP2 run bit set
SC2P

CMP2 passive level set

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data