Regviz

Infineon /XMC4400 /PREF /PCON

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PCON

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Infineon/XMC4500/PREF/PCON#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)IBYP 0 (value1)IINV

IINV=value1, IBYP=value1

Description

Prefetch Configuration Register

Fields

IBYP

Instruction Prefetch Buffer Bypass

0 (value1): Instruction prefetch buffer not bypassed.

1 (value2): Instruction prefetch buffer bypassed.
IINV

Instruction Prefetch Buffer Invalidate

0 (value1): No effect.

1 (value2): Initiate invalidation of entire instruction cache.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data