Infineon /XMC4500 /CAN /CLC

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISR)DISR 0 (DISS)DISS 0 (EDIS)EDIS 0 (SBWE)SBWE

Description

CAN Clock Control Register

Fields

DISR

Module Disable Request Bit

DISS

Module Disable Status Bit

EDIS

Sleep Mode Enable Control

SBWE

Module Suspend Bit Write Enable for OCDS

Links

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