Infineon /XMC4500 /ETH0 /MAC_CONFIGURATION

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Interpret as MAC_CONFIGURATION

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PRELEN 0 (RE)RE 0 (TE)TE 0 (DC)DC 0BL0 (ACS)ACS 0 (DR)DR 0 (IPC)IPC 0 (DM)DM 0 (LM)LM 0 (DO)DO 0 (FES)FES 0 (DCRS)DCRS 0IFG0 (JE)JE 0 (BE)BE 0 (JD)JD 0 (WD)WD 0 (TC)TC 0 (CST)CST 0 (TWOKPE)TWOKPE 0SARC

Description

MAC Configuration Register

Fields

PRELEN

Preamble Length for Transmit Frames

RE

Receiver Enable

TE

Transmitter Enable

DC

Deferral Check

BL

Back-Off Limit

ACS

Automatic Pad or CRC Stripping

DR

Disable Retry

IPC

Checksum Offload

DM

Duplex Mode

LM

Loopback Mode

DO

Disable Receive Own

FES

Speed

DCRS

Disable Carrier Sense During Transmission

IFG

Inter-Frame Gap

JE

Jumbo Frame Enable

BE

Frame Burst Enable

JD

Jabber Disable

WD

Watchdog Disable

TC

Transmit Configuration in RMII

CST

CRC Stripping of Type Frames

TWOKPE

IEEE 802.3as support for 2K packets Enable

SARC

Source Address Insertion or Replacement Control

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