PMTSR

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Interpret as PMTSR

MTENDS2=value1, MTEU2=value1, MTEPPRF=value1, MTEU1=value1, MTEU0=value1, MTEMC=value1, MTUSB=value1, MTSD1=value1, MTENDS1=value1, MTENPS=value1, MTETH0TX=value1, MTETH0RX=value1, MTSD0=value1

Description

Parity Memory Test Select Register

Fields

MTENPS	Test Enable Control for PSRAM 0 (value1): Standard operation 1 (value2): Parity bits under test
MTENDS1	Test Enable Control for DSRAM1 0 (value1): Standard operation 1 (value2): Parity bits under test
MTENDS2	Test Enable Control for DSRAM2 0 (value1): Standard operation 1 (value2): Parity bits under test
MTEU0	Test Enable Control for USIC0 Memory 0 (value1): Standard operation 1 (value2): Parity bits under test
MTEU1	Test Enable Control for USIC1 Memory 0 (value1): Standard operation 1 (value2): Parity bits under test
MTEU2	Test Enable Control for USIC2 Memory 0 (value1): Standard operation 1 (value2): Parity bits under test
MTEMC	Test Enable Control for MultiCAN Memory 0 (value1): Standard operation 1 (value2): Parity bits under test
MTEPPRF	Test Enable Control for PMU Prefetch Memory 0 (value1): Standard operation 1 (value2): Parity bits under test
MTUSB	Test Enable Control for USB Memory 0 (value1): Standard operation 1 (value2): Parity bits under test
MTETH0TX	Test Enable Control for ETH TX Memory 0 (value1): Standard operation 1 (value2): Parity bits under test
MTETH0RX	Test Enable Control for ETH RX Memory 0 (value1): Standard operation 1 (value2): Parity bits under test
MTSD0	Test Enable Control for SDMMC Memory 0 0 (value1): Standard operation 1 (value2): Parity bits under test
MTSD1	Test Enable Control for SDMMC Memory 1 0 (value1): Standard operation 1 (value2): Parity bits under test

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