CMD_CRC_ERR_EN=value1, DATA_END_BIT_ERR_EN=value1, CURRENT_LIMIT_ERR_EN=value1, TARGET_RESP_ERR_EN=value1, CMD_TIMEOUT_ERR_EN=value1, CEATA_ERR_EN=value1, DATA_TIMEOUT_ERR_EN=value1, CMD_IND_ERR_EN=value1, DATA_CRC_ERR_EN=value1, ACMD_ERR_EN=value1, CMD_END_BIT_ERR_EN=value1
Error Interrupt Signal Enable Register
| CMD_TIMEOUT_ERR_EN | Command Timeout Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |
| CMD_CRC_ERR_EN | Command CRC Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |
| CMD_END_BIT_ERR_EN | Command End Bit Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |
| CMD_IND_ERR_EN | Command Index Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |
| DATA_TIMEOUT_ERR_EN | Data Timeout Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |
| DATA_CRC_ERR_EN | Data CRC Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |
| DATA_END_BIT_ERR_EN | Data End Bit Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |
| CURRENT_LIMIT_ERR_EN | Current Limit Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |
| ACMD_ERR_EN | Auto CMD12 Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |
| TARGET_RESP_ERR_EN | Target Response Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |
| CEATA_ERR_EN | Ceata Error Signal Enable 0 (value1): Masked 1 (value2): Enabled |