TRIE=value1, INIT=value1, CCE=value1, ALIE=value1, LECIE=value1
Node Control Register
| INIT | Node Initialization 0 (value1): Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic. 1 (value2): Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set. |
| TRIE | Transfer Interrupt Enable 0 (value1): Transfer interrupt is disabled. 1 (value2): Transfer interrupt is enabled. |
| LECIE | LEC Indicated Error Interrupt Enable 0 (value1): Last error code interrupt is disabled. 1 (value2): Last error code interrupt is enabled. |
| ALIE | Alert Interrupt Enable 0 (value1): Alert interrupt is disabled. 1 (value2): Alert interrupt is enabled. |
| CANDIS | CAN Disable |
| TXDIS | Transmit Disable |
| CCE | Configuration Change Enable 0 (value1): The Bit Timing Register, the Port Control Register, Error Counter Register may only be read. All attempts to modify them are ignored. 1 (value2): The Bit Timing Register, the Port Control Register, Error Counter Register may be read and written. |
| CALM | CAN Analyzer Mode |