Regviz

Infineon /XMC4700 /DSD /OCS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as OCS

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Infineon/XMC4700/DSD/OCS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)SUS0 (SUS_P)SUS_P 0 (value1)SUSSTA

SUS=value1, SUSSTA=value1

Description

OCDS Control and Status Register

Fields

SUS

OCDS Suspend Control

0 (value1): Will not suspend

1 (value2): Hard suspend: Clock is switched off immediately.

2 (value3): Soft suspend channel 0

3 (value4): Soft suspend channel 1

5 (value5): Soft suspend channel 3
SUS_P

SUS Write Protection
SUSSTA

Suspend State

0 (value1): Module is not (yet) suspended

1 (value2): Module is suspended

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data