Infineon /XMC4700 /DSD_CH0 /IWCTR

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Interpret as IWCTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0NVALCNT0 (value1)INTEN 0REPCNT0REPVAL0NVALDIS0 (value1)IWS 0NVALINT

IWS=value1, INTEN=value1

Description

Integration Window Control Register

Fields

NVALCNT

Number of Values Counted

INTEN

Integration Enable

0 (value1): Integration stopped. INTEN is cleared at the end of the integration window, i.e. upon the inverse trigger event transition of the external trigger signal.

1 (value2): Integration enabled. INTEN is set upon the defined trigger event.

REPCNT

Integration Cycle Counter

REPVAL

Number of Integration Cycles

NVALDIS

Number of Values Discarded

IWS

Integration Window SIze

0 (value1): Internal control: stop integrator after REPVAL+1 integration cycles

1 (value2): External control: stop integrator when bit INTEN becomes 0

NVALINT

Number of Values Integrated

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