Infineon /XMC4700 /SDMMC /EN_INT_STATUS_ERR

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Interpret as EN_INT_STATUS_ERR

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)CMD_TIMEOUT_ERR_EN 0 (value1)CMD_CRC_ERR_EN 0 (value1)CMD_END_BIT_ERR_EN 0 (value1)CMD_IND_ERR_EN 0 (value1)DATA_TIMEOUT_ERR_EN 0 (value1)DATA_CRC_ERR_EN 0 (value1)DATA_END_BIT_ERR_EN 0 (value1)CURRENT_LIMIT_ERR_EN 0 (value1)ACMD_ERR_EN 0 (value1)TARGET_RESP_ERR_EN 0 (value1)CEATA_ERR_EN

DATA_CRC_ERR_EN=value1, CMD_IND_ERR_EN=value1, DATA_END_BIT_ERR_EN=value1, TARGET_RESP_ERR_EN=value1, CMD_TIMEOUT_ERR_EN=value1, CMD_END_BIT_ERR_EN=value1, DATA_TIMEOUT_ERR_EN=value1, CEATA_ERR_EN=value1, CURRENT_LIMIT_ERR_EN=value1, CMD_CRC_ERR_EN=value1, ACMD_ERR_EN=value1

Description

Error Interrupt Status Enable Register

Fields

CMD_TIMEOUT_ERR_EN

Command Timeout Error Status Enable

0 (value1): Masked

1 (value2): Enabled

CMD_CRC_ERR_EN

Command CRC Error Status Enable

0 (value1): Masked

1 (value2): Enabled

CMD_END_BIT_ERR_EN

Command End Bit Error Status Enable

0 (value1): Masked

1 (value2): Enabled

CMD_IND_ERR_EN

Command Index Error Status Enable

0 (value1): Masked

1 (value2): Enabled

DATA_TIMEOUT_ERR_EN

Data Timeout Error Status Enable

0 (value1): Masked

1 (value2): Enabled

DATA_CRC_ERR_EN

Data CRC Error Status Enable

0 (value1): Masked

1 (value2): Enabled

DATA_END_BIT_ERR_EN

Data End Bit Error Status Enable

0 (value1): Masked

1 (value2): Enabled

CURRENT_LIMIT_ERR_EN

Current Limit Error Status Enable

0 (value1): Masked

1 (value2): Enabled

ACMD_ERR_EN

Auto CMD12 Error Status Enable

0 (value1): Masked

1 (value2): Enabled

TARGET_RESP_ERR_EN

Target Response Error Status Enable

0 (value1): Masked

1 (value2): Enabled

CEATA_ERR_EN

Ceata Error Status Enable

0 (value1): Masked

1 (value2): Enabled

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