Infineon /XMC4700 /USB0 /HCFG

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Interpret as HCFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FSLSPclkSel 0 (value1)FSLSSupp 0 (DescDMA)DescDMA 0 (value1)FrListEn 0 (PerSchedEna)PerSchedEna

FrListEn=value1, FSLSSupp=value1

Description

Host Configuration Register

Fields

FSLSPclkSel

FS PHY Clock Select

1 (value1): PHY clock is running at 48 MHz

FSLSSupp

FS-Only Support

0 (value1): FS-only, connected device can supports also only FS.

1 (value2): FS-only, even if the connected device can support HS

DescDMA

Enable Scatter/gather DMA in Host mode

FrListEn

Frame List Entries

0 (value1): 8 Entries

1 (value2): 16 Entries

2 (value3): 32 Entries

3 (value4): 64 Entries

PerSchedEna

Enable Periodic Scheduling

Links

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