MCLK=value1, WAFEIEN=value1, SELINV=value1, DX2TIEN=value1, ENDIEN=value1, WAREIEN=value1, WAGEN=value1, DTEN=value1
Protocol Control Register [IIS Mode]
| WAGEN | WA Generation Enable 0 (value1): The IIS can be used as slave. The generation of the word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCR.MCLK. 1 (value2): The IIS can be used as master. The generation of the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCR.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods. |
| DTEN | Data Transfers Enable 0 (value1): The changes of the WA input signal are ignored and no transfers take place. 1 (value2): Transfers are enabled. |
| SELINV | Select Inversion 0 (value1): The SELOx outputs have the same polarity as the WA signal. 1 (value2): The SELOx outputs have the inverted polarity to the WA signal. |
| WAFEIEN | WA Falling Edge Interrupt Enable 0 (value1): A protocol interrupt is not activated if a falling edge of WA is generated. 1 (value2): A protocol interrupt is activated if a falling edge of WA is generated. |
| WAREIEN | WA Rising Edge Interrupt Enable 0 (value1): A protocol interrupt is not activated if a rising edge of WA is generated. 1 (value2): A protocol interrupt is activated if a rising edge of WA is generated. |
| ENDIEN | END Interrupt Enable 0 (value1): A protocol interrupt is not activated. 1 (value2): A protocol interrupt is activated. |
| DX2TIEN | DX2T Interrupt Enable 0 (value1): A protocol interrupt is not generated if DX2T is active. 1 (value2): A protocol interrupt is generated if DX2T is active. |
| TDEL | Transfer Delay |
| MCLK | Master Clock Enable 0 (value1): The MCLK generation is disabled and MCLK is 0. 1 (value2): The MCLK generation is enabled. |