Regviz

Infineon /XMC4800 /ETH0 /MMC_IPC_RECEIVE_INTERRUPT_MASK

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MMC_IPC_RECEIVE_INTERRUPT_MASK

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Infineon/XMC4300/ETH0/MMC_IPC_RECEIVE_INTERRUPT_MASK#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXIPV4GFIM)RXIPV4GFIM 0 (RXIPV4HERFIM)RXIPV4HERFIM 0 (RXIPV4NOPAYFIM)RXIPV4NOPAYFIM 0 (RXIPV4FRAGFIM)RXIPV4FRAGFIM 0 (RXIPV4UDSBLFIM)RXIPV4UDSBLFIM 0 (RXIPV6GFIM)RXIPV6GFIM 0 (RXIPV6HERFIM)RXIPV6HERFIM 0 (RXIPV6NOPAYFIM)RXIPV6NOPAYFIM 0 (RXUDPGFIM)RXUDPGFIM 0 (RXUDPERFIM)RXUDPERFIM 0 (RXTCPGFIM)RXTCPGFIM 0 (RXTCPERFIM)RXTCPERFIM 0 (RXICMPGFIM)RXICMPGFIM 0 (RXICMPERFIM)RXICMPERFIM 0 (RXIPV4GOIM)RXIPV4GOIM 0 (RXIPV4HEROIM)RXIPV4HEROIM 0 (RXIPV4NOPAYOIM)RXIPV4NOPAYOIM 0 (RXIPV4FRAGOIM)RXIPV4FRAGOIM 0 (RXIPV4UDSBLOIM)RXIPV4UDSBLOIM 0 (RXIPV6GOIM)RXIPV6GOIM 0 (RXIPV6HEROIM)RXIPV6HEROIM 0 (RXIPV6NOPAYOIM)RXIPV6NOPAYOIM 0 (RXUDPGOIM)RXUDPGOIM 0 (RXUDPEROIM)RXUDPEROIM 0 (RXTCPGOIM)RXTCPGOIM 0 (RXTCPEROIM)RXTCPEROIM 0 (RXICMPGOIM)RXICMPGOIM 0 (RXICMPEROIM)RXICMPEROIM

Description

MMC Receive Checksum Offload Interrupt Mask Register

Fields

RXIPV4GFIM

MMC Receive IPV4 Good Frame Counter Interrupt Mask
RXIPV4HERFIM

MMC Receive IPV4 Header Error Frame Counter Interrupt Mask
RXIPV4NOPAYFIM

MMC Receive IPV4 No Payload Frame Counter Interrupt Mask
RXIPV4FRAGFIM

MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask
RXIPV4UDSBLFIM

MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask
RXIPV6GFIM

MMC Receive IPV6 Good Frame Counter Interrupt Mask
RXIPV6HERFIM

MMC Receive IPV6 Header Error Frame Counter Interrupt Mask
RXIPV6NOPAYFIM

MMC Receive IPV6 No Payload Frame Counter Interrupt Mask
RXUDPGFIM

MMC Receive UDP Good Frame Counter Interrupt Mask
RXUDPERFIM

MMC Receive UDP Error Frame Counter Interrupt Mask
RXTCPGFIM

MMC Receive TCP Good Frame Counter Interrupt Mask
RXTCPERFIM

MMC Receive TCP Error Frame Counter Interrupt Mask
RXICMPGFIM

MMC Receive ICMP Good Frame Counter Interrupt Mask
RXICMPERFIM

MMC Receive ICMP Error Frame Counter Interrupt Mask
RXIPV4GOIM

MMC Receive IPV4 Good Octet Counter Interrupt Mask
RXIPV4HEROIM

MMC Receive IPV4 Header Error Octet Counter Interrupt Mask
RXIPV4NOPAYOIM

MMC Receive IPV4 No Payload Octet Counter Interrupt Mask
RXIPV4FRAGOIM

MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask
RXIPV4UDSBLOIM

MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask
RXIPV6GOIM

MMC Receive IPV6 Good Octet Counter Interrupt Mask
RXIPV6HEROIM

MMC Receive IPV6 Header Error Octet Counter Interrupt Mask
RXIPV6NOPAYOIM

MMC Receive IPV6 No Payload Octet Counter Interrupt Mask
RXUDPGOIM

MMC Receive UDP Good Octet Counter Interrupt Mask
RXUDPEROIM

MMC Receive UDP Error Octet Counter Interrupt Mask
RXTCPGOIM

MMC Receive TCP Good Octet Counter Interrupt Mask
RXTCPEROIM

MMC Receive TCP Error Octet Counter Interrupt Mask
RXICMPGOIM

MMC Receive ICMP Good Octet Counter Interrupt Mask
RXICMPEROIM

MMC Receive ICMP Error Octet Counter Interrupt Mask

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data