TE=NO, MS=SLAVE, TEN=IGNORE, LB=NORMAL, BEN=IGNORE, PE=NO, EN=Programming_mode, REN=IGNORE, PH=SHIFT, BE=NO, AREN=N_A, PEN=IGNORE, HB=LSB, PO=LOW, RE=NO
Control register
| BM | Data width selection 1 (Const_1): Const_1 15 (Transfer_data): Transfer datawidth is 2 … 16 bits (BM + 1) |
| HB | Heading control 0 (LSB): Transmit/Receive LSB first 1 (MSB): Transmit/Receive MSB first |
| PH | Clock phase control 0 (SHIFT): Transmit data on the leading clock edge, latch on trailing edge 1 (LATCH): Receive data on leading clock edge, shift on trailing edge |
| PO | Clock polarity control 0 (LOW): Idle clock line is low, leading clock edge is low-to-high transition 1 (HIGH): Idle clock line is high, leading clock edge is high-to-low transition |
| LB | Loop back control 0 (NORMAL): Output 1 (LB): Receive input is connected with transmit output (half-duplex mode) |
| TEN | Transmit error enable 0 (IGNORE): Transmit errors 1 (CHECK): Transmit errors |
| REN | Receive error enable 0 (IGNORE): Receive errors 1 (CHECK): Receive errors |
| PEN | Phase error enable 0 (IGNORE): Phase errors 1 (CHECK): Phase errors |
| BEN | Baud rate error enable 0 (IGNORE): Baud rate errors 1 (CHECK): Baud rate errors |
| AREN | Automatic reset enable 0 (N_A): No additional action upon a baud rate error 1 (RESET): The SSC is automatically reset upon a baud rate error |
| MS | Master select 0 (SLAVE): Slave mode. Operate on shift clock received through SCLK 1 (MASTER): Master mode. Generate shift clock and output it through SCLK |
| EN | Enable bit 0 (Programming_mode): Transmission and reception disabled. Access to control bits 1 (Operating_mode): Transmission and reception enabled. Access to status flags and M/S control |
| BC | Bit count field |
| TE | Transmit error flag 0 (NO): Error 1 (ERROR): Transfer starts with the slave’s transmit buffer not being updated |
| RE | Receive error flag 0 (NO): Error 1 (ERROR): Reception completed before the receive buffer was read |
| PE | Phase error flag 0 (NO): Error 1 (ERROR): Received data changes around sampling clock edge |
| BE | Baud rate error flag 0 (NO): Error 1 (ERROR): More than factor 2 or 0.5 between slave’s actual and expected baud rate |
| BSY | Busy flag |