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Keil /AT32F405xx_v2 /TMR10 /DMACTRL

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Interpret as DMACTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADDR0DTB

Description

DMA control register

Fields

ADDR

DMA transfer address offset
DTB

DMA transfer bytes

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data