WDT_EN=dis, RST_FLAG=noEvent, RST_PERIOD=wdt2pow31, INT_EN=dis, INT_PERIOD=wdt2pow31, RST_EN=dis, INT_FLAG=inactive
Watchdog Timer Control Register.
| INT_PERIOD | Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 (wdt2pow31): 2**31 clock cycles. 1 (wdt2pow30): 2**30 clock cycles. 2 (wdt2pow29): 2**29 clock cycles. 3 (wdt2pow28): 2**28 clock cycles. 4 (wdt2pow27): 2^27 clock cycles. 5 (wdt2pow26): 2**26 clock cycles. 6 (wdt2pow25): 2**25 clock cycles. 7 (wdt2pow24): 2**24 clock cycles. 8 (wdt2pow23): 2**23 clock cycles. 9 (wdt2pow22): 2**22 clock cycles. 10 (wdt2pow21): 2**21 clock cycles. 11 (wdt2pow20): 2**20 clock cycles. 12 (wdt2pow19): 2**19 clock cycles. 13 (wdt2pow18): 2**18 clock cycles. 14 (wdt2pow17): 2**17 clock cycles. 15 (wdt2pow16): 2**16 clock cycles. |
| RST_PERIOD | Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 (wdt2pow31): 2**31 clock cycles. 1 (wdt2pow30): 2**30 clock cycles. 2 (wdt2pow29): 2**29 clock cycles. 3 (wdt2pow28): 2**28 clock cycles. 4 (wdt2pow27): 2^27 clock cycles. 5 (wdt2pow26): 2**26 clock cycles. 6 (wdt2pow25): 2**25 clock cycles. 7 (wdt2pow24): 2**24 clock cycles. 8 (wdt2pow23): 2**23 clock cycles. 9 (wdt2pow22): 2**22 clock cycles. 10 (wdt2pow21): 2**21 clock cycles. 11 (wdt2pow20): 2**20 clock cycles. 12 (wdt2pow19): 2**19 clock cycles. 13 (wdt2pow18): 2**18 clock cycles. 14 (wdt2pow17): 2**17 clock cycles. 15 (wdt2pow16): 2**16 clock cycles. |
| WDT_EN | Watchdog Timer Enable. 0 (dis): Disable. 1 (en): Enable. |
| INT_FLAG | Watchdog Timer Interrupt Flag. 0 (inactive): No interrupt is pending. 1 (pending): An interrupt is pending. |
| INT_EN | Watchdog Timer Interrupt Enable. 0 (dis): Disable. 1 (en): Enable. |
| RST_EN | Watchdog Timer Reset Enable. 0 (dis): Disable. 1 (en): Enable. |
| RST_FLAG | Watchdog Timer Reset Flag. 0 (noEvent): The event has not occurred. 1 (occurred): The event has occurred. |