Maxim-Integrated /max32657 /UART /DMA

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Interpret as DMA

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TX_THD_VAL 0 (TX_EN)TX_EN 0RX_THD_VAL 0 (RX_EN)RX_EN

Description

DMA Configuration register

Fields

TX_THD_VAL

TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory.

TX_EN

TX DMA channel enable

RX_THD_VAL

Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory.

RX_EN

RX DMA channel enable

Links

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