Maxim-Integrated /max32660 /UART0 /CTRL1

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Interpret as CTRL1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RX_FIFO_LVL0TX_FIFO_LVL0RTS_FIFO_LVL

Description

Threshold Control register.

Fields

RX_FIFO_LVL

RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.

TX_FIFO_LVL

TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.

RTS_FIFO_LVL

RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.

Links

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