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Maxim-Integrated /max32662 /DMA /INTEN

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Interpret as INTEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)CH0 0 (CH1)CH1 0 (CH2)CH2 0 (CH3)CH3

CH0=dis

Description

DMA Control Register.

Fields

CH0

Channel 0 Interrupt Enable.

0 (dis): Disable.

1 (en): Enable.
CH1

Channel 1 Interrupt Enable.
CH2

Channel 2 Interrupt Enable.
CH3

Channel 3 Interrupt Enable.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk