DNR=respond, FLUSH=not_flushed
Receive Control Register 0.
| DNR | Do Not Respond. 0 (respond): Always respond to address match. 1 (not_respond_rx_fifo_empty): Do not respond to address match when RX_FIFO is not empty. |
| FLUSH | Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. 0 (not_flushed): FIFO not flushed. 1 (flush): Flush RX_FIFO. |
| THD_LVL | Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. |