INACT=256, POST=256, PRE=256
Register for controlling SPI peripheral/Slave Select Timing.
PRE | Slave Select Pre delay 1. 0 (256): 256 system clocks between SS active and first serial clock edge. |
POST | Slave Select Post delay 2. 0 (256): 256 system clocks between last serial clock edge and SS inactive. |
INACT | Slave Select Inactive delay. 0 (256): 256 system clocks between transactions. |