Maxim-Integrated /max32665 /I2C0 /CLK_LO

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Interpret as CLK_LO

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCL_LO

Description

Clock Low Register.

Fields

SCL_LO

Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.

Links

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