Maxim-Integrated /max32665 /SDHC /CLK_CN

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Interpret as CLK_CN

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INTERNAL_CLK_EN)INTERNAL_CLK_EN 0 (INTERNAL_CLK_STABLE)INTERNAL_CLK_STABLE 0 (SD_CLK_EN)SD_CLK_EN 0 (CLK_GEN_SEL)CLK_GEN_SEL 0UPPER_SDCLK_FREQ_SEL 0SDCLK_FREQ_SEL

Description

Clock Control.

Fields

INTERNAL_CLK_EN

Internal Clock Enable.

INTERNAL_CLK_STABLE

Internal Clock Stable.

SD_CLK_EN

SD Clock Enable.

CLK_GEN_SEL

Clock Generator Select.

UPPER_SDCLK_FREQ_SEL

Upper Bits of SDCLK Frequency Select.

SDCLK_FREQ_SEL

SDCLK Frequency Select.

Links

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