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Maxim-Integrated /max32665 /SMON /EXTSCN

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Interpret as EXTSCN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)EXTS_EN0 0 (dis)EXTS_EN1 0 (dis)EXTS_EN2 0 (dis)EXTS_EN3 0 (dis)EXTS_EN4 0 (dis)EXTS_EN5 0EXTCNT0 (freq2000Hz)EXTFRQ 0 (div1)DIVCLK 0 (idle)BUSY 0 (unlocked)LOCK

EXTS_EN2=dis, LOCK=unlocked, EXTS_EN0=dis, EXTFRQ=freq2000Hz, BUSY=idle, EXTS_EN1=dis, EXTS_EN4=dis, DIVCLK=div1, EXTS_EN5=dis, EXTS_EN3=dis

Description

External Sensor Control Register.

Fields

EXTS_EN0

External Sensor Enable for input/output pair 0.

0 (dis): Disable.

1 (en): Enable.
EXTS_EN1

External Sensor Enable for input/output pair 1.

0 (dis): Disable.

1 (en): Enable.
EXTS_EN2

External Sensor Enable for input/output pair 2.

0 (dis): Disable.

1 (en): Enable.
EXTS_EN3

External Sensor Enable for input/output pair 3.

0 (dis): Disable.

1 (en): Enable.
EXTS_EN4

External Sensor Enable for input/output pair 4.

0 (dis): Disable.

1 (en): Enable.
EXTS_EN5

External Sensor Enable for input/output pair 5.

0 (dis): Disable.

1 (en): Enable.
EXTCNT

External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered.
EXTFRQ

External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair.

0 (freq2000Hz): Div 4 (2000Hz).

1 (freq1000Hz): Div 8 (1000Hz).

2 (freq500Hz): Div 16 (500Hz).

3 (freq250Hz): Div 32 (250Hz).

4 (freq125Hz): Div 64 (125Hz).

5 (freq63Hz): Div 128 (63Hz).

6 (freq31Hz): Div 256 (31Hz).

7 (RFU): Reserved. Do not use.
DIVCLK

Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor.

0 (div1): Divide by 1 (8000 Hz).

1 (div2): Divide by 2 (4000 Hz).

2 (div4): Divide by 4 (2000 Hz).

3 (div8): Divide by 8 (1000 Hz).

4 (div16): Divide by 16 (500 Hz).

5 (div32): Divide by 32 (250 Hz).

6 (div64): Divide by 64 (125 Hz).
BUSY

Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain.

0 (idle): Idle.

1 (busy): Update in Progress.
LOCK

Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.

0 (unlocked): Unlocked.

1 (locked): Locked.

Links

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Register Reference

https://github.com/analogdevicesinc/msdk