TX_UN=inactive, RX_OV=inactive
Interrupt Status Register 1.
| RX_OV | Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. 0 (inactive): No Interrupt is Pending. 1 (pending): An interrupt is pending. |
| TX_UN | Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn’t sent a NACK yet). 0 (inactive): No Interrupt is Pending. 1 (pending): An interrupt is pending. |
| START | START Condition Status Flag. |