NACK_FLUSH_DIS=en, FLUSH=not_flushed, GC_ADDR_FLUSH_DIS=en, WR_ADDR_FLUSH_DIS=en, TX_READY_MODE=en, RD_ADDR_FLUSH_DIS=en
Transmit Control Register 0.
| PRELOAD_MODE | Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. |
| TX_READY_MODE | Transmit FIFO Ready Manual Mode. 0 (en): HW control of I2CTXRDY enabled. 1 (dis): HW control of I2CTXRDY disabled. |
| GC_ADDR_FLUSH_DIS | TX FIFO General Call Address Match Auto Flush Disable. 0 (en): Enabled. 1 (dis): Disabled. |
| WR_ADDR_FLUSH_DIS | TX FIFO Slave Address Match Write Auto Flush Disable. 0 (en): Enabled. 1 (dis): Disabled. |
| RD_ADDR_FLUSH_DIS | TX FIFO Slave Address Match Read Auto Flush Disable. 0 (en): Enabled. 1 (dis): Disabled. |
| NACK_FLUSH_DIS | TX FIFO received NACK Auto Flush Disable. 0 (en): Enabled. 1 (dis): Disabled. |
| FLUSH | Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. 0 (not_flushed): FIFO not flushed. 1 (flush): Flush TX_FIFO. |
| THD_VAL | Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. |