Maxim-Integrated /max32670 /SPI0 /SSTIME

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SSTIME

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (256)PRE0 (256)POST0 (256)INACT

PRE=256, POST=256, INACT=256

Description

Register for controlling SPI peripheral/Slave Select Timing.

Fields

PRE

Slave Select Pre delay 1.

0 (256): 256 system clocks between SS active and first serial clock edge.

POST

Slave Select Post delay 2.

0 (256): 256 system clocks between last serial clock edge and SS inactive.

INACT

Slave Select Inactive delay.

0 (256): 256 system clocks between transactions.

Links

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