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Maxim-Integrated /max32675 /DMA /INTFL

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Interpret as INTFL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (inactive)CH0 0 (CH1)CH1 0 (CH2)CH2 0 (CH3)CH3 0 (CH4)CH4 0 (CH5)CH5 0 (CH6)CH6 0 (CH7)CH7

CH0=inactive

Description

DMA Interrupt Register.

Fields

CH0

Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.

0 (inactive): No interrupt is pending.

1 (pending): An interrupt is pending.
CH1
CH2
CH3
CH4
CH5
CH6
CH7

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk