Maxim-Integrated /max32675 /GCR /PCLKDIS1

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Interpret as PCLKDIS1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (en)UART2 0 (TRNG)TRNG 0 (WWDT0)WWDT0 0 (WWDT1)WWDT1 0 (ICC0)ICC0 0 (CRC)CRC 0 (AES)AES 0 (I2C2)I2C2 0 (I2S)I2S

UART2=en

Description

Peripheral Clock Disable.

Fields

UART2

UART2 Disable.

0 (en): Enable.

1 (dis): Disable.

TRNG

TRNG Disable.

WWDT0

WDT0 Disable.

WWDT1

WDT1 Disable.

ICC0

ICACHE Disable.

CRC

CRC Disable.

AES

AES Disable.

I2C2

I2C2 Disable.

I2S

I2S Clock Disable.

Links

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