Maxim-Integrated /max32675 /I2C0 /CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)EN 0 (slave_mode)MST_MODE 0 (dis)GC_ADDR_EN 0 (dis)IRXM_EN 0 (ack)IRXM_ACK 0 (drive_scl_low)SCL_OUT 0 (drive_sda_low)SDA_OUT 0 (SCL)SCL 0 (SDA)SDA 0 (outputs_disable)BB_MODE 0 (write)READ 0 (en)CLKSTR_DIS 0 (dis)ONE_MST_MODE 0 (HS_EN)HS_EN

READ=write, BB_MODE=outputs_disable, SCL_OUT=drive_scl_low, IRXM_ACK=ack, ONE_MST_MODE=dis, IRXM_EN=dis, EN=dis, MST_MODE=slave_mode, CLKSTR_DIS=en, GC_ADDR_EN=dis, SDA_OUT=drive_sda_low

Description

Control Register0.

Fields

EN

I2C Enable.

0 (dis): Disable I2C.

1 (en): enable I2C.

MST_MODE

Master Mode Enable.

0 (slave_mode): Slave Mode.

1 (master_mode): Master Mode.

GC_ADDR_EN

General Call Address Enable.

0 (dis): Ignore Gneral Call Address.

1 (en): Acknowledge general call address.

IRXM_EN

Interactive Receive Mode.

0 (dis): Disable Interactive Receive Mode.

1 (en): Enable Interactive Receive Mode.

IRXM_ACK

Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.

0 (ack): return ACK (pulling SDA LOW).

1 (nack): return NACK (leaving SDA HIGH).

SCL_OUT

SCL Output. This bits control SCL output when SWOE =1.

0 (drive_scl_low): Drive SCL low.

1 (release_scl): Release SCL.

SDA_OUT

SDA Output. This bits control SDA output when SWOE = 1.

0 (drive_sda_low): Drive SDA low.

1 (release_sda): Release SDA.

SCL

SCL status. This bit reflects the logic gate of SCL signal.

SDA

SDA status. THis bit reflects the logic gate of SDA signal.

BB_MODE

Software Output Enable.

0 (outputs_disable): I2C Outputs SCLO and SDAO disabled.

1 (outputs_enable): I2C Outputs SCLO and SDAO enabled.

READ

Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.

0 (write): Write.

1 (read): Read.

CLKSTR_DIS

This bit will disable slave clock stretching when set.

0 (en): Slave clock stretching enabled.

1 (dis): Slave clock stretching disabled.

ONE_MST_MODE

SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.

0 (dis): Standard open-drain operation: drive low for 0, Hi-Z for 1

1 (en): Non-standard push-pull operation: drive low for 0, drive high for 1

HS_EN

High speed mode enable

Links

()