Maxim-Integrated /max32675 /MCR /RST

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RST

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (lptmr0)lptmr0 0 (lptmr1)lptmr1 0 (lpuart0)lpuart0 0 (rtc)rtc

Description

Reset control register 0.

Fields

lptmr0

Setting this bit will reset LPTMR0.

1 (rst): Reset LPTMR0.

lptmr1

Setting this bit will reset LPTMR1.

1 (rst): Reset LPTMR1.

lpuart0

Setting this bit will reset LPUART0.

1 (rst): Reset LPUART0.

rtc

Setting this bit will reset the Real-Time Clock.

1 (rst): Reset Real-Time Clock.

Links

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