TX_FIFO_EN=dis, DMA_RX_EN=dis, DMA_TX_EN=DIS, RX_FIFO_EN=DIS
Register for controlling DMA.
| TX_THD_VAL | Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. |
| TX_FIFO_EN | Transmit FIFO enabled for SPI transactions. 0 (dis): Transmit FIFO is not enabled. 1 (en): Transmit FIFO is enabled. |
| TX_FLUSH | Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 1 (CLEAR): Clear the Transmit FIFO, clears any pending TX FIFO status. |
| TX_LVL | Count of entries in TX FIFO. |
| DMA_TX_EN | TX DMA Enable. 0 (DIS): TX DMA requests are disabled, andy pending DMA requests are cleared. 1 (en): TX DMA requests are enabled. |
| RX_THD_VAL | Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. |
| RX_FIFO_EN | Receive FIFO enabled for SPI transactions. 0 (DIS): Receive FIFO is not enabled. 1 (en): Receive FIFO is enabled. |
| RX_FLUSH | Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 1 (CLEAR): Clear the Receive FIFO, clears any pending RX FIFO status. |
| RX_LVL | Count of entries in RX FIFO. |
| DMA_RX_EN | RX DMA Enable. 0 (dis): RX DMA requests are disabled, any pending DMA requests are cleared. 1 (en): RX DMA requests are enabled. |