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Maxim-Integrated /max32680 /FLC /CLKDIV

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Interpret as CLKDIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIV

Description

Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.

Fields

CLKDIV

Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.

Links

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Register Reference

https://github.com/analogdevicesinc/msdk