Maxim-Integrated /max32680 /GCR /PCLKDIV

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Interpret as PCLKDIV

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADCFRQ0 (div2)CNNCLKDIV 0 (system)CNNCLKSEL

CNNCLKDIV=div2, CNNCLKSEL=system

Description

Peripheral Clock Divider.

Fields

ADCFRQ

ADC clock Frequency. These bits define the ADC clock frequency. fADC = fPCLK / (ADCFRQ)

CNNCLKDIV

CNN Clock Divider.

0 (div2): undefined

1 (div4): undefined

2 (div8): undefined

3 (div16): undefined

4 (div1): undefined

CNNCLKSEL

CNN Clock Select.

0 (system): undefined

1 (IBRO60): undefined

Links

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