CCHK=complete, ICC0_FLUSH=normal, CHKRES=pass, FLASH_PAGE_FLIP=normal
System Control.
| BSTAPEN | Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE. |
| FLASH_PAGE_FLIP | Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 0 (normal): Physical layout matches logical layout. 1 (swapped): Bottom half mapped to logical top half and vice versa. |
| ICC0_FLUSH | Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 0 (normal): Normal Code Cache Operation 1 (flush): Code Caches and CPU instruction buffer are flushed |
| ROMDONE | ROM_DONE status. Used to disable SWD interface during system initialization procedure |
| CCHK | Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 0 (complete): No operation/complete. 1 (start): Start operation. |
| SWD_DIS | Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set). |
| CHKRES | ROM Checksum Result. This bit is only valid when CHKRD=1. 0 (pass): ROM Checksum Correct. 1 (fail): ROM Checksum Fail. |
| OVR | Operating Voltage Range. |