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Maxim-Integrated /max32680 /PWRSEQ /LPCN

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Interpret as LPCN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)RAMRET0 0 (dis)RAMRET1 0 (dis)RAMRET2 0 (dis)RAMRET3 0 (LPMCLKSEL)LPMCLKSEL 0 (LPMFAST)LPMFAST 0 (on)BG_DIS 0 (LPWKST_CLR)LPWKST_CLR

BG_DIS=on, RAMRET3=dis, RAMRET2=dis, RAMRET0=dis, RAMRET1=dis

Description

Low Power Control Register.

Fields

RAMRET0

System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit.

0 (dis): Disable Ram Retention.

1 (en): Enable System RAM 0 retention.
RAMRET1

System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit.

0 (dis): Disable Ram Retention.

1 (en): Enable System RAM 1 retention.
RAMRET2

System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit.

0 (dis): Disable Ram Retention.

1 (en): Enable System RAM 2 retention.
RAMRET3

System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit.

0 (dis): Disable Ram Retention.

1 (en): Enable System RAM 3 retention.
LPMCLKSEL

Low Power Mode APB Clock Select.
LPMFAST

Low Power Mode Clock Select.
BG_DIS

Bandgap OFF. This controls the System Bandgap in DeepSleep mode.

0 (on): Bandgap is always ON.

1 (off): Bandgap is OFF in DeepSleep mode (default).
LPWKST_CLR

Low Power Wakeup Status Register Clear

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk