SS_CTRL=DEASSERT, MST_MODE=dis, SS_IO=output, EN=dis
Register for controlling SPI peripheral.
| EN | SPI Enable. 0 (dis): SPI is disabled. 1 (en): SPI is enabled. |
| MST_MODE | Master Mode Enable. 0 (dis): SPI is Slave mode. 1 (en): SPI is Master mode. |
| SS_IO | Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 0 (output): Slave select 0 is output. 1 (input): Slave Select 0 is input, only valid if MMEN=1. |
| START | Start Transmit. 1 (start): Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. |
| SS_CTRL | Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. 0 (DEASSERT): SPI De-asserts Slave Select at the end of a transaction. 1 (ASSERT): SPI leaves Slave Select asserted at the end of a transaction. |
| SS_ACTIVE | Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. 1 (SS0): SS0 is selected. 2 (SS1): SS1 is selected. 4 (SS2): SS2 is selected. 8 (SS3): SS3 is selected. |