Maxim-Integrated /max32680 /SPI0 /CTRL2

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Interpret as CTRL2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Rising_Edge)CLKPHA 0 (Normal)CLKPOL 0 (16)NUMBITS0 (Mono)DATA_WIDTH 0 (dis)THREE_WIRE 0SS_POL

CLKPHA=Rising_Edge, DATA_WIDTH=Mono, NUMBITS=16, THREE_WIRE=dis, CLKPOL=Normal

Description

Register for controlling SPI peripheral.

Fields

CLKPHA

Clock Phase.

0 (Rising_Edge): Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2

1 (Falling_Edge): Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3

CLKPOL

Clock Polarity.

0 (Normal): Normal Clock. Use when in SPI Mode 0 and Mode 1

1 (Inverted): Inverted Clock. Use when in SPI Mode 2 and Mode 3

NUMBITS

Number of Bits per character.

0 (16): 16 bits per character.

1 (1): 1 bits per character.

2 (2): 2 bits per character.

3 (3): 3 bits per character.

4 (4): 4 bits per character.

5 (5): 5 bits per character.

6 (6): 6 bits per character.

7 (7): 7 bits per character.

8 (8): 8 bits per character.

9 (9): 9 bits per character.

10 (10): 10 bits per character.

11 (11): 11 bits per character.

12 (12): 12 bits per character.

13 (13): 13 bits per character.

14 (14): 14 bits per character.

15 (15): 15 bits per character.

DATA_WIDTH

SPI Data width.

0 (Mono): 1 data pin.

1 (Dual): 2 data pins.

2 (Quad): 4 data pins.

THREE_WIRE

Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.

0 (dis): Use four wire mode (Mono only).

1 (en): Use three wire mode.

SS_POL

Slave Select Polarity, each Slave Select can have unique polarity.

1 (SS0_high): SS0 active high.

2 (SS1_high): SS1 active high.

4 (SS2_high): SS2 active high.

8 (SS3_high): SS3 active high.

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