Regviz

Maxim-Integrated /max32680 /WDT /RST

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RST

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Maxim-Integrated/max32672/WDT/RST#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESET

Description

Windowed Watchdog Timer Reset Register.

Fields

RESET

Writing the watchdog counter ‘reset sequence’ to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled.

90 (seq1): The second value to be written to reset the WDT.

165 (seq0): The first value to be written to reset the WDT.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk