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Maxim-Integrated /max78000 /FCR /URVCTRL

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Interpret as URVCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MEMSEL)MEMSEL 0 (IFLUSHEN)IFLUSHEN

Description

RISC-V Control Register.

Fields

MEMSEL

RAM2, RAM3 exclusive ownership.
IFLUSHEN

URV instruction flush enable.

Links

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Register Reference

https://github.com/analogdevicesinc/msdk