Maxim-Integrated /max78000 /GCR /PCLKDIS0

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Interpret as PCLKDIS0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (en)GPIO0 0 (GPIO1)GPIO1 0 (DMA)DMA 0 (SPI1)SPI1 0 (UART0)UART0 0 (UART1)UART1 0 (I2C0)I2C0 0 (TMR0)TMR0 0 (TMR1)TMR1 0 (TMR2)TMR2 0 (TMR3)TMR3 0 (ADC)ADC 0 (CNN)CNN 0 (I2C1)I2C1 0 (PT)PT

GPIO0=en

Description

Peripheral Clock Disable.

Fields

GPIO0

GPIO0 Clock Disable.

0 (en): enable it.

1 (dis): disable it.

GPIO1

GPIO1 Clock Disable.

DMA

DMA Clock Disable.

SPI1

SPI 1 Clock Disable.

UART0

UART 0 Clock Disable.

UART1

UART 1 Clock Disable.

I2C0

I2C 0 Clock Disable.

TMR0

Timer 0 Clock Disable.

TMR1

Timer 1 Clock Disable.

TMR2

Timer 2 Clock Disable.

TMR3

Timer 3 Clock Disable.

ADC

ADC Clock Disable.

CNN

CNN Clock Disable.

I2C1

I2C 1 Clock Disable.

PT

Pluse Train Clock Disable.

Links

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