Maxim-Integrated /max78000 /GCR /RST0

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Interpret as RST0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (reset_done)DMA 0 (WDT0)WDT0 0 (GPIO0)GPIO0 0 (GPIO1)GPIO1 0 (TMR0)TMR0 0 (TMR1)TMR1 0 (TMR2)TMR2 0 (TMR3)TMR3 0 (UART0)UART0 0 (UART1)UART1 0 (SPI1)SPI1 0 (I2C0)I2C0 0 (RTC)RTC 0 (SMPHR)SMPHR 0 (TRNG)TRNG 0 (CNN)CNN 0 (ADC)ADC 0 (UART2)UART2 0 (SOFT)SOFT 0 (PERIPH)PERIPH 0 (SYS)SYS

DMA=reset_done

Description

Reset.

Fields

DMA

DMA Reset.

0 (reset_done): Reset complete.

1 (busy): Starts Reset or indicates reset in progress.

WDT0

Watchdog Timer 0 Reset.

GPIO0

GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.

GPIO1

GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.

TMR0

Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks.

TMR1

Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks.

TMR2

Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks.

TMR3

Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks.

UART0

UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks.

UART1

UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks.

SPI1

SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks.

I2C0

I2C 0 Reset.

RTC

Real Time Clock Reset.

SMPHR

Semaphore Reset.

TRNG

TRNG Reset. This reset is only available during the manufacture testing phase.

CNN

CNN Reset.

ADC

ADC Reset.

UART2

UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.

SOFT

Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.

PERIPH

Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.

SYS

System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.

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