CLKDIV_A=DIV_BY_1, CLKDIV_B=DIV_BY_1, MODE_A=ONE_SHOT, MODE_B=ONE_SHOT
Timer Control Register.
| MODE_A | Mode Select for Timer A 0 (ONE_SHOT): One-Shot Mode 1 (CONTINUOUS): Continuous Mode 2 (COUNTER): Counter Mode 3 (PWM): PWM Mode 4 (CAPTURE): Capture Mode 5 (COMPARE): Compare Mode 6 (GATED): Gated Mode 7 (CAPCOMP): Capture/Compare Mode 8 (DUAL_EDGE): Dual Edge Capture Mode 14 (IGATED): Inactive Gated Mode |
| CLKDIV_A | Clock Divider Select for Timer A 0 (DIV_BY_1): Prescaler Divide-By-1 1 (DIV_BY_2): Prescaler Divide-By-2 2 (DIV_BY_4): Prescaler Divide-By-4 3 (DIV_BY_8): Prescaler Divide-By-8 4 (DIV_BY_16): Prescaler Divide-By-16 5 (DIV_BY_32): Prescaler Divide-By-32 6 (DIV_BY_64): Prescaler Divide-By-64 7 (DIV_BY_128): Prescaler Divide-By-128 8 (DIV_BY_256): Prescaler Divide-By-256 9 (DIV_BY_512): Prescaler Divide-By-512 10 (DIV_BY_1024): Prescaler Divide-By-1024 11 (DIV_BY_2048): Prescaler Divide-By-2048 12 (DIV_BY_4096): TBD |
| POL_A | Timer Polarity for Timer A |
| PWMSYNC_A | PWM Synchronization Mode for Timer A |
| NOLHPOL_A | PWM Phase A (Non-Overlapping High) Polarity for Timer A |
| NOLLPOL_A | PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A |
| PWMCKBD_A | PWM Phase A-Prime Output Disable for Timer A |
| RST_A | Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. |
| CLKEN_A | Write 1 to Enable CLK_TMR for Timer A |
| EN_A | Enable for Timer A |
| MODE_B | Mode Select for Timer B 0 (ONE_SHOT): One-Shot Mode 1 (CONTINUOUS): Continuous Mode 2 (COUNTER): Counter Mode 3 (PWM): PWM Mode 4 (CAPTURE): Capture Mode 5 (COMPARE): Compare Mode 6 (GATED): Gated Mode 7 (CAPCOMP): Capture/Compare Mode 8 (DUAL_EDGE): Dual Edge Capture Mode 14 (IGATED): Inactive Gated Mode |
| CLKDIV_B | Clock Divider Select for Timer B 0 (DIV_BY_1): Prescaler Divide-By-1 1 (DIV_BY_2): Prescaler Divide-By-2 2 (DIV_BY_4): Prescaler Divide-By-4 3 (DIV_BY_8): Prescaler Divide-By-8 4 (DIV_BY_16): Prescaler Divide-By-16 5 (DIV_BY_32): Prescaler Divide-By-32 6 (DIV_BY_64): Prescaler Divide-By-64 7 (DIV_BY_128): Prescaler Divide-By-128 8 (DIV_BY_256): Prescaler Divide-By-256 9 (DIV_BY_512): Prescaler Divide-By-512 10 (DIV_BY_1024): Prescaler Divide-By-1024 11 (DIV_BY_2048): Prescaler Divide-By-2048 12 (DIV_BY_4096): TBD |
| POL_B | Timer Polarity for Timer B |
| PWMSYNC_B | PWM Synchronization Mode for Timer B |
| NOLHPOL_B | PWM Phase A (Non-Overlapping High) Polarity for Timer B |
| NOLLPOL_B | PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B |
| PWMCKBD_B | PWM Phase A-Prime Output Disable for Timer B |
| RST_B | Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. |
| CLKEN_B | Write 1 to Enable CLK_TMR for Timer B |
| EN_B | Enable for Timer B |