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Maxim-Integrated /max78000 /UART /FIFO

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Interpret as FIFO

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DATA0 (RX_PAR)RX_PAR

Description

FIFO Read/Write register

Fields

DATA

Load/unload location for TX and RX FIFO buffers.
RX_PAR

Parity error flag for next byte to be read from FIFO.

Links

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Register Reference

https://github.com/analogdevicesinc/msdk